Random access memories (RAMs) typically come in standard presized building block packages. These packages are addressable over a set of address leads, which leads, in turn, are connected to an address bus. In a typical graphics processing system, several different types of memories may be employed, some having 8 leads and some having 9, 10 or 11 leads. As technology changes, the number of addressing leads will continue to change also.
The address cycle of a typical processing system accesses the memory by providing an address having perhaps 32 bits. Some of the bits refer to the row address and some of the bits refer to the column address. To conserve space on the memory, the same leads are used for both the row and the column address information. This can be so since a time multiplexing scheme is used whereby first the bits from the bus corresponding to the row address are clocked to the memory and then the bits on the bus corresponding to the column are clocked to the memory. This works since the positions in the bus word where the row and column bits are located are fixed and thus the leads can be permanently associated with the proper corresponding address bit.
This system works fine, except when the same processor and bus handle memories having different numbers of address leads. The problem is as follows. Assume that both an 8-bit and a 9-bit address memory are connected to a common bus. Assume also that bits 0-7 of the address represent the column address for the 8-bit memory with bits 8-15 representing the row address. Under this condition the memory leads would be connected to the bus such that address bits 0 and 8 (through appropriate logic circuits) would be connected to memory lead 0 and address bits 1 and 9 connected to memory lead 1. Thus, address bits 7 and 15 would be connected through buffers, to memory lead 7.
Now assume that the 9-bit memory uses address bits 0-8 for the column address and bits 9-17 for the row address. The memory, following traditional logic, would be wired to the bus as discussed above such that in this fashion address bits 0 and 9 would go to memory lead 0 while address bits 8 and 17 would go to memory lead 8.
Now comes an 8 bit address directed to the 8-bit memory. The row portion typically comes during the first phase of the write cycle, so address bits 8-15 are gated into memory via memory leads 0-7. During the next phase of the memory cycle, address bits 0-7 are gated to memory, also on memory leads 0-7. There is no problem so far since all of the possible combinations of addresses on the 8-bit address are uniquely associated with a different memory lead, or with the same lead at different times. The memory is accessed properly and can be fully utilized.
Now comes a 9 bit address directed to the 9 bit memory. The row portion comes first and is presented to the memory on memory inputs 0-8. However, at this time the processor has not determined if the address is an 8 bit or 9 bit address. Thus, unless some special action were to be taken, address bits 8-16 (the same as before with one added) would be presented to memory leads 0-8. Address bit 8, however is, as discussed above, actually part of the 9 bit column address. Thus, problems result when a system attempts to concurrently use memories having different addressing capabilities.
In the prior art, in order to accomplish addressing to different size memories in the same system, complex external multiplexing logic is required.
Thus a need exists in the art for an arrangement which will allow a single bus to contain the addresses for various size RAMs, with only a minimum of external logic.